Botond Kirei – „PAElib 2.0: Power&Area Aware Modeling of CMOS Digital Circuits in VHDL”, prezentat la conferinta IEEE TSP 2020 (43rd International Conference on Telecommunications and Signal Processing)

de | 7 iulie 2020
Niciun comentariu

Botond Kirei – „PAElib 2.0: Power&Area Aware Modeling of CMOS Digital Circuits in VHDL”, prezentat la conferinta IEEE TSP 2020 (43rd International Conference on Telecommunications and Signal Processing)